a) Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly to a ferroelectric memory device whose memory cell is constituted of a field electric transistor and two ferroelectric capacitors.
b) Description of the Related Art
Dynamic random access memories (DRAM) have taken the main trend of semiconductor storage devices. DRAM is a volatile memory whose storage contents are extinguished when a power supply stops. Nonvolatile memories whose storage contents are not extinguished even if a power supply stops, are being developed.
Recently, as one type of nonvolatile memories, ferroelectric memories using ferroelectric material have drawn attention. Ferroelectric memories are roughly divided into two types. One type detects the storage contents from a change in the storage capacitance of a ferroelectric capacitor, and the other type detects the storage contents from a change in the resistance of semiconductor to be caused by residual polarization of a ferroelectric film.
A ferroelectric memory of the former type includes 2Tr-2C type and 1TR-1C type. 2Tr-2C type stores one-bit data by using two transistors and two capacitors, whereas 1Tr-1C type stores one-bit data by using one transistor and one capacitor. As a ferroelectric memory of the latter type, 1Tr type is known which has a gate insulating film made of ferroelectric material.
As ferroelectric memories of 2Tr-2C type, memories having 64 k bits are realized in practice. It is, however, difficult to increase an integration degree because two transistors and two capacitors are required to store one-bit data. Ferroelectric memories of 1Tr-1C type are easy to raise an integration degree. However, reference cells are likely to be deteriorated as operation time becomes long, so that it is difficult to improve reliability and realize long lifetime.
Ferroelectric memories of 1Tr type are still in the stage that the operation thereof only at a cell level is confirmed, and the drive method of a cell array is not yet established. In addition, a source line as well as a word line and a bit line is necessary and isolation of a back gate is necessary, so that the cell area is difficult to be reduced.